System Idle
Ready to Start
Follow the H446 FDE cycle. We include the transfer from MDR to CIR and the use of the Control Bus.
A-Level Context
The cycle includes registers like the CIR and specific bus signaling.
CPU Core
PC
001
MAR
---
MDR
---
CIR
---
Accumulator
0
Control Unit (CU)
ALU
Main Memory
001: LDR #25
002: ADD #5
... ...
System Architecture
H446 Factor: Determines the number of cycles per second. Limited by the heat produced (thermal throttling).
H446 Factor: Each core can process a different instruction. Doubling cores potentially doubles throughput if software is optimized for multicore.
H446 Advanced Concept: Overlapping stages of the FDE cycle. While instruction 1 is executing, instruction 2 is being decoded, and instruction 3 is being fetched.
Increases throughput by completing more cycles in the same clock pulse.
H446 Factor: Fast, expensive memory inside the CPU. Reduces the "Von Neumann Bottleneck" by reducing RAM access.
Total Effective Throughput
0
Instructions Per Second (IPS)
Active Pipeline Overlap (3-Stage)
Pipeline inactive (Sequential Processing)