J277 CPU Cycles and Efficiency

Interactive Fetch-Decode-Execute Cycle & Performance Simulator

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Step-by-Step Cycle

Press "Next Step" to begin the cycle. We start by fetching the instruction from RAM.

Current Stage:

READY

Key Component Info:

Select a step to see how components like the ALU or CU are used.
Central Processing Unit
Prog. Counter
001
MAR
---
MDR
---
Accumulator
0
Control Unit (CU)
Decodes & Orchestrates
ALU
Calculations & Logic
Main Memory (RAM)
001: ADD #10
002: STR #005
003: HALT
BUS ARCHITECTURE
Address Bus Data Bus